7 search results - page 1 / 2 » High-performance scheduling algorithm for partially parallel... |
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partia...
TIT
2008
13 years 8 months ago
2008
Abstract--Low-Density Parity-Check (LDPC) codes are usually decoded by running an iterative belief-propagation algorithm over the factor graph of the code. In the traditional messa...
ICDCS
1996
IEEE
14 years 21 days ago
1996
IEEE
Efficiently scheduling parallel tasks on to the processors of a shared-memory multiprocessor is critical to achieving high performance. Given perfect information at compile-time, ...
HPDC
2003
IEEE
14 years 1 months ago
2003
IEEE
Divisible workload applications arise in many fields of science and engineering. They can be parallelized in master-worker fashion and relevant scheduling strategies have been pr...