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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 10 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
ISPASS
2005
IEEE
15 years 10 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
ITCC
2005
IEEE
15 years 10 months ago
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography
1 Table lookups are one of the most frequently-used operations in symmetric-key ciphers. Particularly in the newer algorithms such as the Advanced Encryption Standard (AES), we fr...
A. Murat Fiskiran, Ruby B. Lee
MSS
2005
IEEE
175views Hardware» more  MSS 2005»
15 years 10 months ago
High Performance Storage System Scalability: Architecture, Implementation and Experience
The High Performance Storage System (HPSS) provides scalable hierarchical storage management (HSM), archive, and file system services. Its design, implementation and current domin...
Richard W. Watson
QSHINE
2005
IEEE
15 years 10 months ago
On Increasing End-to-End Throughput in Wireless Ad Hoc Networks
One of the main characteristics of wireless ad hoc networks is their node-centric broadcast nature of communication, leading to interferences and spatial contention between adjace...
Zongpeng Li, Baochun Li