183 search results - page 35 / 37 » History-based memory mode prediction for improving memory pe... |
LCTRTS
2001
Springer
13 years 12 months ago
2001
Springer
Strict control over the scheduling and execution of processor resources is essential for many fixed-priority real-time applications. To facilitate this common requirement, the Re...
ICS
2003
Tsinghua U.
14 years 18 days ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
CGO
2004
IEEE
13 years 11 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
LOPSTR
2005
Springer
14 years 27 days ago
2005
Springer
Abstract. Several models for context-sensitive analysis of modular programs have been proposed, each with different characteristics and representing different trade-offs. The ad...
IJCNN
2008
IEEE
14 years 1 months ago
2008
IEEE
— Nowadays, huge amounts of information from different industrial processes are stored into databases and companies can improve their production efficiency by mining some new kn...