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ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
14 years 1 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
SPLC
2004
13 years 9 months ago
Dynamic Configuration of Software Product Lines in ArchJava
Abstract. This paper considers the use of a state-of-the-art, generalpurpose, component programming language, specifically ArchJava, to implement software product lines. Component ...
Sebastian Pavel, Jacques Noyé, Jean-Claude ...
ICTAC
2010
Springer
13 years 5 months ago
Mechanized Verification with Sharing
We consider software verification of imperative programs by theorem proving in higher-order separation logic. Of particular interest are the difficulties of encoding and reasoning ...
J. Gregory Malecha, Greg Morrisett
ICSEA
2007
IEEE
14 years 1 months ago
Test Data Generation from UML State Machine Diagrams using GAs
Automatic test data generation helps testers to validate software against user requirements more easily. Test data can be generated from many sources; for example, experience of t...
Chartchai Doungsa-ard, Keshav P. Dahal, M. Alamgir...
KBSE
2009
IEEE
14 years 2 months ago
Inferring Method Effect Summaries for Nested Heap Regions
Effect systems are important for reasoning about the side effects of a program. Although effect systems have been around for decades, they have not been widely adopted in practice...
Mohsen Vakilian, Danny Dig, Robert L. Bocchino Jr....