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ENTCS
2007
13 years 10 months ago
2007
This paper is part of a comprehensive approach to debugging for functional logic languages. The basic idea of the whole project is to trace the execution of functional logic progr...
INFORMATICALT
1998
13 years 9 months ago
1998
This paper describes a method how to represent and build a reusable VHDL component. By that component we can, for example, describe a family of the relative VHDL models. To represe...
CMPB
2008
13 years 8 months ago
2008
Recently, in a series of papers, a method based on pseudo-values has been proposed for direct regression modeling of the survival function, the restricted mean and cumulative inci...
LPAR
2010
Springer
13 years 8 months ago
2010
Springer
Traditionally, the full verification of a program's functional correctness has been obtained with pen and paper or with interactive proof assistants, whereas only reduced ver...
AMOST
2005
ACM
14 years 3 months ago
2005
ACM
We consider the problem of generating a set of test cases from a black box specification. We focus on stress testing, i.e. picking test cases that seem most likely to reveal prog...