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» How to Parallelize Sequential Processes
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HPCA
2012
IEEE
12 years 4 months ago
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chi
Lowering supply voltage is one of the most effective techniques for reducing microprocessor power consumption. Unfortunately, at low voltages, chips are very sensitive to process ...
Timothy N. Miller, Xiang Pan, Renji Thomas, Naser ...
CAMP
2005
IEEE
14 years 2 months ago
Speeding-up NCC-Based Template Matching Using Parallel Multimedia Instructions
— This paper describes the mapping of a recently introduced template matching algorithm based on the Normalized Cross Correlation (NCC) on a general purpose processor endowed wit...
Luigi di Stefano, Stefano Mattoccia, Federico Tomb...
IPPS
2008
IEEE
14 years 3 months ago
Reducing the run-time of MCMC programs by multithreading on SMP architectures
The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov Chain Mont...
Jonathan M. R. Byrd, Stephen A. Jarvis, A. H. Bhal...
PADS
1996
ACM
14 years 1 months ago
Experiments in Automated Load Balancing
One of the promises of parallelized discrete-event simulation is that it might provide significant speedups over sequential simulation. In reality, high performance cannot be achi...
Linda F. Wilson, David M. Nicol
INTENSIVE
2009
IEEE
14 years 3 months ago
Accelerating K-Means on the Graphics Processor via CUDA
In this paper an optimized k-means implementation on the graphics processing unit (GPU) is presented. NVIDIA’s Compute Unified Device Architecture (CUDA), available from the G8...
Mario Zechner, Michael Granitzer