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GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
14 years 5 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
ATVA
2007
Springer
226views Hardware» more  ATVA 2007»
14 years 5 months ago
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
David Walter, Scott Little, Chris J. Myers
CHARME
2005
Springer
176views Hardware» more  CHARME 2005»
14 years 4 months ago
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment
Abstract. Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision D...
Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P...
CPAIOR
2008
Springer
14 years 19 days ago
Stochastic Satisfiability Modulo Theories for Non-linear Arithmetic
Abstract. The stochastic satisfiability modulo theories (SSMT) problem is a generalization of the SMT problem on existential and randomized (aka. stochastic) quantification over di...
Tino Teige, Martin Fränzle
IJCSS
2007
133views more  IJCSS 2007»
13 years 10 months ago
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
This paper presents a low power driven synthesis framework for the unique class of nonregenerative Boolean Read-Once Functions (BROF). A two-pronged approach is adopted, where the...
P. Balasubramanian, S. Theja