713 search results - page 4 / 143 » Hybrid transactional memory |
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
MASCOTS
2010
13 years 9 months ago
2010
In this paper, we develop a queuing theory based analytical model to evaluate the performance of transactional memory. Based on the statistical characteristics observed on actual e...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
With the latest high-end computing nodes combining shared-memory multiprocessing with hardware multithreading, new scheduling policies are necessary for workloads consisting of mu...
ADBIS
1997
Springer
13 years 11 months ago
1997
Springer
In this paper we consider real-time concurrency control for the nested transaction model. We analyze problems that have pure optimistic and pessimistic approaches. As the solution...