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» IXM2: A Parallel Associative Processor
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IPPS
2007
IEEE
14 years 1 months ago
A Key-based Adaptive Transactional Memory Executor
Software transactional memory systems enable a programmer to easily write concurrent data structures such as lists, trees, hashtables, and graphs, where non-conflicting operation...
Tongxin Bai, Xipeng Shen, Chengliang Zhang, Willia...
ICS
2000
Tsinghua U.
13 years 11 months ago
A low-complexity issue logic
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
Ramon Canal, Antonio González
IPPS
2009
IEEE
14 years 2 months ago
A component-based framework for the Cell Broadband Engine
With the increasing trend of microprocessor manufacturers to rely on parallelism to increase their products’ performance, there is an associated increasing need for simple techn...
Timothy D. R. Hartley, Ümit V. Çataly&...
CASES
2000
ACM
13 years 11 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
ANSS
2002
IEEE
14 years 15 days ago
Gang Scheduling Performance on a Cluster of Non-Dedicated Workstations
Clusters of workstations have emerged as a costeffective solution to high performance computing problem. To take advantage of any opportunities, however, effective scheduling tech...
Helen D. Karatza