Sciweavers

759 search results - page 82 / 152
» Identifying Modeling Errors in Signatures by Model Checking
Sort
View
FMCAD
2009
Springer
14 years 3 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
CORR
2010
Springer
144views Education» more  CORR 2010»
13 years 9 months ago
Algorithmic Verification of Single-Pass List Processing Programs
We introduce streaming data string transducers that map input data strings to output data strings in a single left-to-right pass in linear time. Data strings are (unbounded) seque...
Rajeev Alur, Pavol Cerný
ICSE
2007
IEEE-ACM
14 years 9 months ago
Feedback-Directed Random Test Generation
We present a technique that improves random test generation by incorporating feedback obtained from executing test inputs as they are created. Our technique builds inputs incremen...
Carlos Pacheco, Shuvendu K. Lahiri, Michael D. Ern...
CAV
2004
Springer
151views Hardware» more  CAV 2004»
14 years 24 days ago
QB or Not QB: An Efficient Execution Verification Tool for Memory Orderings
We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models--an important step during post-silicon verification of multipro...
Ganesh Gopalakrishnan, Yue Yang, Hemanthkumar Siva...
CAV
2008
Springer
96views Hardware» more  CAV 2008»
13 years 11 months ago
Implied Set Closure and Its Application to Memory Consistency Verification
Hangal et. al. [3] have developed a procedure to check if an instance of the execution of a shared memory multiprocessor program, is consistent with the Total Store Order (TSO) mem...
Surender Baswana, Shashank K. Mehta, Vishal Powar