72 search results - page 1 / 15 » Impact of memory hierarchy on program partitioning and sched... |
HICSS
1995
IEEE
14 years 2 months ago
1995
IEEE
IPPS
2007
IEEE
14 years 5 months ago
2007
IEEE
In this paper, we present a mechanism for automatic management of the memory hierarchy, including secondary storage, in the context of a global address space parallel programming ...
IPPS
2006
IEEE
14 years 5 months ago
2006
IEEE
The development of efficient parallel out-of-core applications is often tedious, because of the need to explicitly manage the movement of data between files and data structures ...
CASES
2001
ACM
14 years 2 months ago
2001
ACM
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
ICASSP
2008
IEEE
14 years 5 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...