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ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 9 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
DAC
2000
ACM
14 years 8 months ago
COSY communication IP's
The Esprit/OMI-COSY project defines transaction-levels to set-up the exchange of IP's in separating function from architecture and body-behavior from proprietary interfaces. ...
Erwin A. de Kock, Frédéric Pé...
ISCA
2009
IEEE
186views Hardware» more  ISCA 2009»
14 years 2 months ago
Application-aware deadlock-free oblivious routing
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
Michel A. Kinsy, Myong Hyon Cho, Tina Wen, G. Edwa...
INTEGRATION
2008
183views more  INTEGRATION 2008»
13 years 7 months ago
Network-on-Chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated component...
David Atienza, Federico Angiolini, Srinivasan Mura...
MIS
2008
Springer
191views Multimedia» more  MIS 2008»
13 years 7 months ago
QoS management and control for an all-IP WiMAX network architecture: Design, implementation and evaluation
The IEEE 802.16 standard provides a specification for a fixed and mobile broadband wireless access system, offering high data rate transmission of multimedia services with differen...
Thomas Michael Bohnert, Marco Castrucci, Nicola Ci...