In the context of a reconfigurable transport protocol framework, we propose a QoS-aware Transport Protocol (QSTP), specifically designed to operate over QoS-enabled networks with ...
Guillaume Jourjon, Emmanuel Lochin, Patrick S&eacu...
We describe a digital circuit synthesis algorithm specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use this algorithm as ...
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
In this work, we present the novel idea of route normalization by correcting on the fly routing traffic on behalf of a local router to protect the local network from malicious a...
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...