801 search results - page 32 / 161 » Implementation and Use of Transactional Memory with Dynamic ... |
FTCS
1997
13 years 9 months ago
1997
This paper presents robust emulation of multi-writer/multi-reader registers in message-passing systems using dynamic quorum con gurations. In addition to processor and link failur...
IBMRD
2006
13 years 7 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing threads. The memory scheduling algorithm should resolve memory contention...
DASFAA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper investigates the problem of writing data to passive RFID tag memory and proposes a reprocessing model for assuring the atomicity and durability of writing transactions i...