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POPL
2010
ACM
16 years 21 days ago
Automatically Generating Instruction Selectors Using Declarative Machine Descriptions
Despite years of work on retargetable compilers, creating a good, reliable back end for an optimizing compiler still entails a lot of hard work. Moreover, a critical component of ...
João Dias, Norman Ramsey
PPOPP
2010
ACM
16 years 17 days ago
Lazy binary-splitting: a run-time adaptive work-stealing scheduler
We present Lazy Binary Splitting (LBS), a user-level scheduler of nested parallelism for shared-memory multiprocessors that builds on existing Eager Binary Splitting work-stealing...
Alexandros Tzannes, George C. Caragea, Rajeev Baru...
112
Voted
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 6 days ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
128
Voted
WWW
2010
ACM
15 years 10 months ago
A scalable machine-learning approach for semi-structured named entity recognition
Named entity recognition studies the problem of locating and classifying parts of free text into a set of predefined categories. Although extensive research has focused on the de...
Utku Irmak, Reiner Kraft
CGO
2010
IEEE
15 years 10 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
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