Sciweavers

884 search results - page 169 / 177
» Implementation of the MLP Kernel
Sort
View
HPCC
2009
Springer
14 years 1 months ago
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory
Abstract--Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier. However, to be efficient, underlying TM system should protect only...
Sutirtha Sanyal, Sourav Roy, Adrián Cristal...
EMSOFT
2006
Springer
14 years 1 months ago
Multi-level software reconfiguration for sensor networks
In-situ reconfiguration of software is indispensable in embedded networked sensing systems. It is required for re-tasking a deployed network, fixing bugs, introducing new features...
Rahul Balani, Chih-Chieh Han, Ram Kumar Rengaswamy...
CASES
2001
ACM
14 years 1 months ago
A system-on-a-chip lock cache with task preemption support
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
Bilge Saglam Akgul, Jaehwan Lee, Vincent John Moon...
IWAN
2000
Springer
14 years 1 months ago
A Flexible IP Active Networks Architecture
This paper presents the main concepts of the IST Project FAIN "Future Active IP Networks" [10], a three-year collaborative research project, whose main task is to develo...
Alex Galis, Bernhard Plattner, Jonathan M. Smith, ...
LCTRTS
2000
Springer
14 years 1 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross