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» Implementing Optimizations at Decode Time
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ATS
2001
IEEE
137views Hardware» more  ATS 2001»
13 years 11 months ago
Compaction Schemes with Minimum Test Application Time
Testing embedded cores in a System-on-a-chip necessitates the use of a Test Access Mechanism, which provides for transportation of the test data between the chip and the core I/Os...
Ozgur Sinanoglu, Alex Orailoglu
TC
2010
13 years 2 months ago
Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
Tweakable enciphering schemes are length preserving block cipher modes of operation that provide a strong pseudo-random permutation. It has been suggested that these schemes can b...
Cuauhtemoc Mancillas-López, Debrup Chakrabo...
ICCCN
2008
IEEE
14 years 2 months ago
Instrumentation and Analysis of MPI Queue Times on the SeaStar High-Performance Network
—Understanding the communication behavior and network resource usage of parallel applications is critical to achieving high performance and scalability on systems with tens of th...
Ron Brightwell, Kevin T. Pedretti, Kurt B. Ferreir...
WSC
1998
13 years 9 months ago
Parallel Implementation of a Molecular Dynamics Simulation Program
We have taken a NIST molecular dynamics simulation program (md3), which was configured as a single sequential process running on a CRAY C90 vector supercomputer, and parallelized ...
Alan Mink, Christophe Bailly
CLUSTER
2006
IEEE
13 years 8 months ago
Optimizing MPI collective communication by orthogonal structures
Many parallel applications from scientific computing use MPI collective communication operations to collect or distribute data. Since the execution times of these communication op...
Matthias Kühnemann, Thomas Rauber, Gudula R&u...