Sciweavers

857 search results - page 133 / 172
» Implementing a STARI chip
Sort
View
GLVLSI
2007
IEEE
167views VLSI» more  GLVLSI 2007»
14 years 2 months ago
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
Dariusz Kania
ICC
2007
IEEE
14 years 2 months ago
Power Managed Packet Switching
— High power dissipation in packet switches and routers is fast turning into a key problem, owing to increasing line speeds and decreasing chip sizes. To address this issue, we i...
Aditya Dua, Benjamin Yolken, Nicholas Bambos
ISCA
2007
IEEE
128views Hardware» more  ISCA 2007»
14 years 2 months ago
Performance and security lessons learned from virtualizing the alpha processor
Virtualization has become much more important throughout the computer industry both to improve security and to support multiple workloads on the same hardware with effective isola...
Paul A. Karger
CP
2007
Springer
14 years 2 months ago
Scheduling Conditional Task Graphs
The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications o...
Michele Lombardi, Michela Milano
EUROCRYPT
2007
Springer
14 years 2 months ago
Non-wafer-Scale Sieving Hardware for the NFS: Another Attempt to Cope with 1024-Bit
Significant progress in the design of special purpose hardware for supporting the Number Field Sieve (NFS) has been made. From a practical cryptanalytic point of view, however, no...
Willi Geiselmann, Rainer Steinwandt