857 search results - page 141 / 172 » Implementing a STARI chip |
HOTI
2002
IEEE
14 years 1 months ago
2002
IEEE
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...
WACV
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper describes design and implementation of a vision based platform for automated refueling tasks. The platform is an autonomous docking system in principle, with the specif...
SPAA
2010
ACM
14 years 1 months ago
2010
ACM
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
DNA
2001
Springer
14 years 29 days ago
2001
Springer
In the universal DNA chip method, target RNAs are mapped onto a set of DNA tags. Parallel hybridization of these tags with an indexed, complementary antitag array then provides an ...