Sciweavers

857 search results - page 3 / 172
» Implementing a STARI chip
Sort
View
FPL
2006
Springer
147views Hardware» more  FPL 2006»
13 years 11 months ago
Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
High-throughput decoder for low-density parity-check code
— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regula...
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Iken...
HICSS
2002
IEEE
109views Biometrics» more  HICSS 2002»
14 years 8 days ago
Embedding Self-Management and Generic Learning Support into Courseware Structures
Traditional Computer-Aided Teaching and Learning (CAT/CAL) environments in multimedia-based teleeducation do not empower knowledge consumers (trainees, students etc.) to practice ...
Andreas Auinger, Christian Stary
IJNS
2000
80views more  IJNS 2000»
13 years 7 months ago
VLSI Implementation of Neural Networks
Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more compl...
Bogdan M. Wilamowski, J. Binfet, M. O. Kaynak
TPDS
2010
260views more  TPDS 2010»
13 years 5 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear