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ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
14 years 15 days ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
CVPR
2010
IEEE
14 years 28 days ago
Efficient Joint 2D and 3D Palmprint Matching with Alignment Refinement
Palmprint verification is a relatively new but promising personal authentication technique for its high accuracy and fast matching speed. Two dimensional (2D) palmprint recognitio...
Wei Li, Lei Zhang, david Zhang, Guangming Lu, Jing...
ANCS
2008
ACM
13 years 9 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
ANCS
2006
ACM
14 years 1 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
DAC
2005
ACM
13 years 9 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...