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GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
14 years 3 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
ICASSP
2008
IEEE
14 years 3 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
ICDM
2008
IEEE
183views Data Mining» more  ICDM 2008»
14 years 3 months ago
Collaborative Filtering for Implicit Feedback Datasets
A common task of recommender systems is to improve customer experience through personalized recommendations based on prior implicit feedback. These systems passively track differe...
Yifan Hu, Yehuda Koren, Chris Volinsky
WCNC
2008
IEEE
14 years 3 months ago
Intelligent Weather Systems with Fuzzy Logic Controller for Satellite Networks
— Weather attenuations can have a distorting effect on signal fidelity above 10 GHz that lead to excessive digital transmission error. This loss of signal is commonly referred to...
Kamal Harb, Changcheng Huang, Anand Srinivasan, Br...
ICIP
2007
IEEE
14 years 3 months ago
Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding Systems
Significant power savings can be achieved on voltage/frequency configurable platforms by dynamically adapting the frequency and voltage according to the workload (complexity). Vid...
Emrah Akyol, Mihaela van der Schaar