319 search results - page 3 / 64 » Improved Model Checking of Hierarchical Systems |
ISVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
ACSAC
2010
IEEE
13 years 7 months ago
2010
IEEE
Code injection continues to pose a serious threat to computer systems. Among existing solutions, W X is a notable approach to prevent the execution of injected code. In this paper...
CAV
2012
Springer
12 years 7 days ago
2012
Springer
Real-life systems are usually hard to control, due to their complicated structures, quantitative time factors and even stochastic behaviors. In this work, we present a model checke...
TASE
2008
IEEE
14 years 4 months ago
2008
IEEE
Verification techniques like SAT-based bounded model checking have been successfully applied to a variety of system models. Applying bounded model checking to compositional proce...
ACL
2010
13 years 7 months ago
2010
In hierarchical phrase-based SMT systems, statistical models are integrated to guide the hierarchical rule selection for better translation performance. Previous work mainly focus...