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RTAS
2005
IEEE
14 years 1 months ago
Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications
Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while s...
Christian Poellabauer, Leo Singleton, Karsten Schw...
RTAS
2006
IEEE
14 years 1 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
TC
1998
13 years 7 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
SAS
2009
Springer
214views Formal Methods» more  SAS 2009»
14 years 8 months ago
Abstract Interpretation of FIFO Replacement
Interpretation of FIFO Replacement Daniel Grund and Jan Reineke Saarland University, Saarbr?ucken, Germany In hard real-time systems, the execution time of programs must be bounded...
Daniel Grund, Jan Reineke
TPCTC
2010
Springer
147views Hardware» more  TPCTC 2010»
13 years 2 months ago
Assessing and Optimizing Microarchitectural Performance of Event Processing Systems
Abstract. Event Processing (EP) systems are being progressively used in business critical applications in domains such as algorithmic trading, supply chain management, production m...
Marcelo R. N. Mendes, Pedro Bizarro, Paulo Marques