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» Improvements for the Symbolic Verification of Timed Automata
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FORTE
2007
14 years 10 days ago
Improvements for the Symbolic Verification of Timed Automata
Rongjie Yan, Guangyuan Li, Wenliang Zhang, Yunquan...
FORMATS
2006
Springer
14 years 2 months ago
Symbolic Robustness Analysis of Timed Automata
We propose a symbolic algorithm for the analysis of the robustness of timed automata, that is the correctness of the model in presence of small drifts on the clocks or imprecision ...
Conrado Daws, Piotr Kordy
FORMATS
2004
Springer
14 years 2 months ago
Modeling and Verification of a Fault-Tolerant Real-Time Startup Protocol Using Calendar Automata
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...
Bruno Dutertre, Maria Sorea
FORMATS
2007
Springer
14 years 2 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
SDL
2001
125views Hardware» more  SDL 2001»
14 years 7 days ago
Verification of Quantitative Temporal Properties of SDL Specifications
Abstract. We describe an approach for the verification of quantitative temporal properties of SDL specifications, which adapts techniques developed for timed automata [2]. With res...
Iulian Ober, Alain Kerbrat