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ICS
1998
Tsinghua U.
14 years 2 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
SBACPAD
2003
IEEE
75views Hardware» more  SBACPAD 2003»
14 years 3 months ago
The Limits of Speculative Trace Reuse on Deeply Pipelined Processors
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
Maurício L. Pilla, Amarildo T. da Costa, Fe...
TC
2008
13 years 9 months ago
Adaptive Fault Management of Parallel Applications for High-Performance Computing
As the scale of high-performance computing (HPC) continues to grow, failure resilience of parallel applications becomes crucial. In this paper, we present FT-Pro, an adaptive fault...
Zhiling Lan, Yawei Li
GECCO
2003
Springer
160views Optimization» more  GECCO 2003»
14 years 3 months ago
Using Genetic Algorithms for Data Mining Optimization in an Educational Web-Based System
This paper presents an approach for classifying students in order to predict their final grade based on features extracted from logged data in an education web-based system. A comb...
Behrouz Minaei-Bidgoli, William F. Punch
WSC
2004
13 years 11 months ago
Estimating Efficacy of Progressive Planning for Air Traffic Flow Management
Air traffic flow management (TFM) is a set of processes and procedures which seek to balance the demand for airspace resources with the capacity of these resources. Examples of re...
Lynne Fellman, James S. DeArmon, Kelly A. Connolly