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HPCA
2011
IEEE
12 years 10 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ASPLOS
1998
ACM
13 years 11 months ago
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
Walter Lee, Rajeev Barua, Matthew Frank, Devabhakt...
ICS
1998
Tsinghua U.
13 years 11 months ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
CIKM
2008
Springer
13 years 9 months ago
A sparse gaussian processes classification framework for fast tag suggestions
Tagged data is rapidly becoming more available on the World Wide Web. Web sites which populate tagging services offer a good way for Internet users to share their knowledge. An in...
Yang Song, Lu Zhang 0007, C. Lee Giles
CISS
2010
IEEE
12 years 10 months ago
Self-organizing Dynamic Fractional Frequency Reuse on the uplink of OFDMA systems
Reverse link (or uplink) performance of cellular systems is becoming increasingly important with the emergence of new uplink-bandwidth intensive applications such as Video Share [...
Balaji Rengarajan, Alexander L. Stolyar, Harish Vi...