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» Improving Java performance using hardware translation
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IEEEPACT
2008
IEEE
14 years 1 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
CONCURRENCY
2000
101views more  CONCURRENCY 2000»
13 years 7 months ago
Jaguar: enabling efficient communication and I/O in Java
Implementing efficient communication and I/O mechanisms in Java requires both fast access to lowlevel system resources (such as network and raw disk interfaces) and direct manipul...
Matt Welsh, David E. Culler
CASES
2000
ACM
13 years 11 months ago
A code generation framework for Java component-based designs
In this paper, we describe a software architecture supporting code generation from within Ptolemy II. Ptolemy II is a componentbased design tool intended for embedded and real-tim...
Jeff Tsay, Christopher Hylands, Edward Lee
PODC
2009
ACM
14 years 4 months ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve
CF
2009
ACM
14 years 1 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt