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» Improving Java performance using hardware translation
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MICRO
1995
IEEE
97views Hardware» more  MICRO 1995»
13 years 11 months ago
Improving CISC instruction decoding performance using a fill unit
Current superscalar processors, both RISC and CISC, require substantial instruction fetch and decode bandwidth to keep multiple functional units utilized. While CISC instructions ...
Mark Smotherman, Manoj Franklin
SIES
2008
IEEE
14 years 1 months ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
IWMM
2009
Springer
127views Hardware» more  IWMM 2009»
14 years 1 months ago
Investigating the effects of using different nursery sizing policies on performance
In this paper, we investigate the effects of using three different nursery sizing policies on overall and garbage collection performances. As part of our investigation, we modify ...
Xiaohua Guan, Witawas Srisa-an, ChengHuan Jia
IWMM
2007
Springer
110views Hardware» more  IWMM 2007»
14 years 1 months ago
Path: page access tracking to improve memory management
Traditionally, operating systems use a coarse approximation of memory accesses to implement memory management algorithms by monitoring page faults or scanning page table entries. ...
Reza Azimi, Livio Soares, Michael Stumm, Thomas Wa...
MICRO
1997
IEEE
108views Hardware» more  MICRO 1997»
13 years 11 months ago
Improving the Accuracy and Performance of Memory Communication Through Renaming
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...
Gary S. Tyson, Todd M. Austin