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» Improving Java performance using hardware translation
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167
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RTAS
2009
IEEE
15 years 9 months ago
Real-Time Video Surveillance over IEEE 802.11 Mesh Networks
In recent years, there has been an increase in video surveillance systems in public and private environments due to a heightened sense of security. The next generation of surveill...
Arvind Kandhalu, Anthony Rowe, Ragunathan Rajkumar...
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
15 years 7 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
115
Voted
IEEEPACT
2008
IEEE
15 years 9 months ago
Adaptive insertion policies for managing shared caches
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...
Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qu...
120
Voted
PLDI
1999
ACM
15 years 6 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
132
Voted
IEEEPACT
2005
IEEE
15 years 8 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove