315 search results - page 48 / 63 » Improving Performance by Branch Reordering |
111
Voted
HPCA
2004
IEEE
16 years 4 months ago
2004
IEEE
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
142
Voted
PCI
2005
Springer
15 years 9 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
116
Voted
JSAC
2000
15 years 3 months ago
2000
Enhanced Data Rates for Global Evolution (EDGE) is currently being standardized as an evolution of GSM in Europe and of IS-136 in the United States as an air interface for high spe...
125
Voted
LCTRTS
2009
Springer
15 years 10 months ago
2009
Springer
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
120
Voted
CF
2006
ACM
15 years 9 months ago
2006
ACM
There is a continuous research effort devoted to overcome the memory wall problem. Prefetching is one of the most frequently used techniques. A prefetch mechanism anticipates the ...