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» Improving Performance by Branch Reordering
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IPPS
2007
IEEE
14 years 1 months ago
Optimizing Inter-Nest Data Locality Using Loop Splitting and Reordering
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
Sofiane Naci
IEEEPACT
2006
IEEE
14 years 1 months ago
Adaptive reorder buffers for SMT processors
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev
COLING
2010
13 years 2 months ago
Constituent Reordering and Syntax Models for English-to-Japanese Statistical Machine Translation
We present a constituent parsing-based reordering technique that improves the performance of the state-of-the-art English-to-Japanese phrase translation system that includes disto...
Young-Suk Lee, Bing Zhao, Xiaoqian Luo
EMNLP
2011
12 years 7 months ago
Training a Parser for Machine Translation Reordering
We propose a simple training regime that can improve the extrinsic performance of a parser, given only a corpus of sentences and a way to automatically evaluate the extrinsic qual...
Jason Katz-Brown, Slav Petrov, Ryan T. McDonald, F...
ISCA
2007
IEEE
115views Hardware» more  ISCA 2007»
14 years 1 months ago
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...
Hyesoon Kim, José A. Joao, Onur Mutlu, Chan...