328 search results - page 11 / 66 » Improving Performance of Small On-Chip Instruction Caches |
ASPLOS
1987
ACM
13 years 11 months ago
1987
ACM
One potentialdisadvantage of a machine with a reduced instruction. set is that object programs may be substantially larger than those for a machine with a richer, more complex ins...
ACMMSP
2004
ACM
14 years 1 months ago
2004
ACM
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
IEEEPACT
1999
IEEE
13 years 12 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...