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CODES
2000
IEEE
14 years 12 hour ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
IPPS
2000
IEEE
13 years 12 months ago
Study of a Multilevel Approach to Partitioning for Parallel Logic Simulation
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
Swaminathan Subramanian, Dhananjai Madhava Rao, Ph...
INFOCOM
1999
IEEE
13 years 12 months ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...
SIBGRAPI
1999
IEEE
13 years 12 months ago
Real-Time Shadow Generation Using BSP Trees and Stencil Buffers
This paper describes a real-time shadow generation algorithm for polygonal environments illuminated by movable point light sources. The main goal is to quickly reduce the number o...
Harlen Costa Batagelo, Ilaim Costa Júnior
ICLP
1997
Springer
13 years 11 months ago
The Complexity of Model Checking in Modal Event Calculi
Kowalski and Sergot’s Event Calculus (EC) is a simple temporal formalism that, given a set of event occurrences, derives the maximal validity intervals (MVIs) over which propert...
Iliano Cervesato, Massimo Franceschet, Angelo Mont...