1045 search results - page 44 / 209 » Improving SHA-2 Hardware Implementations |
RSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rende...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
MIMO (Multi Input Multi Output) wireless communication system is an innovative solution to improve the bandwidth efficiency by exploiting multipath-richness of the propagation envi...
CGO
2005
IEEE
14 years 2 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...