5523 search results - page 60 / 1105 » Improving application performance with hardware data structu... |
ASPLOS
1998
ACM
13 years 12 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
DELTA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and impro...
IPPS
1996
IEEE
13 years 12 months ago
1996
IEEE
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
CDC
2009
IEEE
13 years 11 months ago
2009
IEEE
Abstract-- Dataflow representations of Digital Signal Processing (DSP) software have been developing since the 1980's. They have proven to be useful in identifying bottlenecks...
ICIP
2009
IEEE
13 years 5 months ago
2009
IEEE
A novel framework for spatially estimating unknown image data is presented. Common applications include inpainting, concealment of transmission errors, prediction in video coding,...