59 search results - page 5 / 12 » Improving distributed memory applications testing by message... |
IWCC
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, we present techniques and algorithms to improve the performance of various communication patterns on message-passing platforms where, for reasons of safety, user-le...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we use Dijkstra’s algorithm as a challenging, hard to parallelize paradigm to test the efficacy of several parallelization techniques in a multicore architecture....
SC
2005
ACM
14 years 1 months ago
2005
ACM
Many emerging large-scale data science applications require searching large graphs distributed across multiple memories and processors. This paper presents a distributed breadth...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...