1001 search results - page 13 / 201 » Improving memory hierarchy performance for irregular applica... |
APLAS
2006
ACM
14 years 14 days ago
2006
ACM
We present a method to visit all nodes in a forest of data structures while taking into account object placement. We call the technique a Localized Tracing Scheme as it improves lo...
IPPS
1996
IEEE
14 years 27 days ago
1996
IEEE
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
PPAM
2005
Springer
14 years 2 months ago
2005
Springer
Abstract. We present the way in which we adapt data and computations to the underlying memory hierarchy by means of a hierarchical data structure known as hypermatrix. The applicat...
PDP
2011
IEEE
13 years 12 days ago
2011
IEEE
—This paper proposes a parallelization scheme for parameter sweep (PS) applications using the compute unified device architecture (CUDA). Our scheme focuses on PS applications w...
LCPC
1999
Springer
14 years 1 months ago
1999
Springer
Abstract. As the speed gap between CPU and memory widens, memory hierarchy has become the performance bottleneck for most applications because of both the high latency and low band...