1001 search results - page 15 / 201 » Improving memory hierarchy performance for irregular applica... |
SIGMETRICS
1992
ACM
14 years 24 days ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
Achieving good performance on a modern machine with a multi-level memory hierarchy, and in particular on a machine with software-managed memories, requires precise tuning of progr...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
IISWC
2009
IEEE
14 years 3 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
HPCC
2011
Springer
12 years 8 months ago
2011
Springer
— Mapping of parallel applications on the network topology is becoming increasingly important on large supercomputers. Topology aware mapping can reduce the hops traveled by mess...