1001 search results - page 72 / 201 » Improving memory hierarchy performance for irregular applica... |
222
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ISCA
2012
IEEE
13 years 8 months ago
2012
IEEE
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
149
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SBACPAD
2006
IEEE
16 years 8 days ago
2006
IEEE
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
132
Voted
DAC
2005
ACM
16 years 7 months ago
2005
ACM
Dual-execution/checkpointing based transient error tolerance techniques have been widely used in the high-end mission critical systems. These techniques, however, are not very att...
187
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CF
2007
ACM
15 years 10 months ago
2007
ACM
In this paper we describe a new technique, called pipeline spectroscopy, and use it to measure the cost of each cache miss. The cost of a miss is displayed (graphed) as a histogra...
162
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MICRO
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...