Sciweavers

271 search results - page 21 / 55
» Improving the Average Delay of Sorting
Sort
View
SPAA
1997
ACM
13 years 12 months ago
Pipelining with Futures
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
Guy E. Blelloch, Margaret Reid-Miller
ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
14 years 2 months ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
GRID
2008
Springer
13 years 7 months ago
Statistical Analysis and Modeling of Jobs in a Grid Environment
The existence of good probabilistic models for the job arrival process and the delay components introduced at different stages of job processing in a Grid environment is important ...
Kostas Christodoulopoulos, Vasileios Gkamas, Emman...
IEEEPACT
2008
IEEE
14 years 2 months ago
Scalable and reliable communication for hardware transactional memory
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen ...
DAC
2003
ACM
14 years 8 months ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan