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ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw
VLSISP
2008
108views more  VLSISP 2008»
13 years 7 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 1 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
NIPS
2007
13 years 9 months ago
Measuring Neural Synchrony by Message Passing
A novel approach to measure the interdependence of two time series is proposed, referred to as “stochastic event synchrony” (SES); it quantifies the alignment of two point pr...
Justin Dauwels, François B. Vialatte, Tomas...
WWW
2008
ACM
14 years 8 months ago
Rogue access point detection using segmental TCP jitter
Rogue Access Points (RAPs) pose serious security threats to local networks. An analytic model of prior probability distribution of Segmental TCP Jitter (STJ) is deduced from the m...
Gaogang Xie, Tingting He, Guangxing Zhang