Sciweavers

271 search results - page 40 / 55
» Improving the Average Delay of Sorting
Sort
View
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
14 years 4 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
INFOCOM
2009
IEEE
14 years 2 months ago
Link Scheduling with QoS Guarantee for Wireless Relay Networks
—The emerging wireless relay networks (WRNs) are expected to provide significant improvement on throughput and extension of coverage area for next-generation wireless systems. W...
Chi-Yao Hong, Ai-Chun Pang
ADHOCNETS
2009
Springer
14 years 2 months ago
Distributed Spectrum Sharing for Video Streaming in Cognitive Radio Ad Hoc Networks
A distributed joint routing and spectrum sharing algorithm for video streaming applications over cognitive radio ad hoc networks is proposed in this article. The proposed cross-lay...
Lei Ding, Scott Pudlewski, Tommaso Melodia, Stella...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara