Sciweavers

68 search results - page 4 / 14
» Improving the performance of speculatively parallel applicat...
Sort
View
IISWC
2009
IEEE
14 years 2 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee
PLDI
2012
ACM
11 years 10 months ago
Speculative separation for privatization and reductions
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
Nick P. Johnson, Hanjun Kim, Prakash Prabhu, Ayal ...
ICS
2011
Tsinghua U.
12 years 11 months ago
Predictive coordination of multiple on-chip resources for chip multiprocessors
Efficient on-chip resource management is crucial for Chip Multiprocessors (CMP) to achieve high resource utilization and enforce system-level performance objectives. Existing mul...
Jian Chen, Lizy Kurian John
IISWC
2008
IEEE
14 years 1 months ago
Characterizing and improving the performance of Intel Threading Building Blocks
Abstract— The Intel Threading Building Blocks (TBB) runtime library [1] is a popular C++ parallelization environment [2][3] that offers a set of methods and templates for creatin...
Gilberto Contreras, Margaret Martonosi
PDP
2008
IEEE
14 years 1 months ago
Just-In-Time Scheduling for Loop-based Speculative Parallelization
Scheduling for speculative parallelization is a problem that remained unsolved despite its importance. Simple methods such as Fixed-Size Chunking (FSC) need several ‘dry-runs’...
Diego R. Llanos Ferraris, David Orden, Belé...