1036 search results - page 131 / 208 » Incompleteness of Behavioral Logics |
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Protocol conversion involves the use of a converter to control communication between two or more protocols such that desired system-level specifications can be satisfied. We invest...
CADE
2007
Springer
14 years 9 months ago
2007
Springer
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
TACAS
2007
Springer
14 years 3 months ago
2007
Springer
For specifying and verifying branching-time requirements, a reactive system is traditionally modeled as a labeled tree, where a path in the tree encodes a possible execution of the...
PPDP
2005
Springer
14 years 2 months ago
2005
Springer
fects are statically generated program abstractions, that can be model checked for verification of assertions in a temporal program logic. In this paper we develop a type and eff...
FPL
2006
Springer
14 years 18 days ago
2006
Springer
A Field Programmable Gate Array (FPGA), when used as a platform for implementing special-purpose computing architectures, offers the potential for increased functional parallelism...