30 search results - page 3 / 6 » Increased Scalability and Power Efficiency by Using Multiple... |
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we ex...
BMCBI
2011
12 years 10 months ago
2011
Background: Pairwise sequence alignment methods are widely used in biological research. The increasing number of sequences is perceived as one of the upcoming challenges for seque...
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
FPGA
2004
ACM
14 years 15 days ago
2004
ACM
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
FPGA
2009
ACM
14 years 1 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...