Sciweavers

661 search results - page 16 / 133
» Increasing Processor Performance by Implementing Deeper Pipe...
Sort
View
ASPLOS
1991
ACM
13 years 11 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
SAMOS
2005
Springer
14 years 26 days ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He
FPL
2009
Springer
135views Hardware» more  FPL 2009»
14 years 4 hour ago
Fast critical sections via thread scheduling for FPGA-based multithreaded processors
As FPGA-based systems including soft processors become increasingly common, we are motivated to better understand the architectural trade-offs and improve the efficiency of these...
Martin Labrecque, J. Gregory Steffan
IPPS
2009
IEEE
14 years 2 months ago
Building a parallel pipelined external memory algorithm library
Large and fast hard disks for little money have enabled the processing of huge amounts of data on a single machine. For this purpose, the well-established STXXL library provides a...
Andreas Beckmann, Roman Dementiev, Johannes Single...
MTV
2003
IEEE
109views Hardware» more  MTV 2003»
14 years 19 days ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt