Sciweavers

661 search results - page 24 / 133
» Increasing Processor Performance by Implementing Deeper Pipe...
Sort
View
ISCAPDCS
2001
13 years 8 months ago
A Multiple Blocks Fetch Engine for High Performance Superscalar Processors
The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one bra...
Yung-Chung Wu, Jong-Jiann Shieh
CHES
1999
Springer
91views Cryptology» more  CHES 1999»
13 years 11 months ago
A High-Performance Flexible Architecture for Cryptography
Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementat...
R. Reed Taylor, Seth Copen Goldstein
IPPS
2005
IEEE
14 years 1 months ago
Broadcast Trees for Heterogeneous Platforms
In this paper, we deal with broadcasting on heterogeneous platforms. Typically, the message to be broadcast is split into several slices, which are sent by the source processor in...
Olivier Beaumont, Loris Marchal, Yves Robert
IEICET
2006
84views more  IEICET 2006»
13 years 7 months ago
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4
Abstract. This paper discusses the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing s...
Mitsuru Matsui, Sayaka Fukuda
JCP
2008
119views more  JCP 2008»
13 years 7 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi