1139 search results - page 115 / 228 » Increasing the throughput of HomePNA |
ICS
1995
Tsinghua U.
14 years 18 days ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
WSC
2007
13 years 11 months ago
2007
This paper presents a new job release methodology, WIPLOAD Control, especially in semiconductor wafer fabrication environment. The performance of the proposed methodology is evalu...
WSC
2008
13 years 11 months ago
2008
Experienced and wise industrial engineering educators and practitioners have long understood that industrial engineering is a coherent discipline encompassing techniques that work...
ANCS
2008
ACM
13 years 11 months ago
2008
ACM
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...
FPGA
2008
ACM
13 years 10 months ago
2008
ACM
This paper presents high-throughput techniques for implementing FSM based string matching hardware on FPGAs. By taking advantage of the fact that string matching operations for di...