5623 search results - page 995 / 1125 » Incremental Mechanism Design |
165
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EMSOFT
2007
Springer
15 years 10 months ago
2007
Springer
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
122
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IWMM
2007
Springer
15 years 10 months ago
2007
Springer
Traditionally, operating systems use a coarse approximation of memory accesses to implement memory management algorithms by monitoring page faults or scanning page table entries. ...
204
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VLDB
2007
ACM
15 years 10 months ago
2007
ACM
This tutorial presents the definition, the models and the techniques of location privacy from the data privacy perspective. By reviewing and revising the state of art research in ...
126
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IEEEPACT
2006
IEEE
15 years 10 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
155
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IPCCC
2006
IEEE
15 years 10 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...